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![PDF] A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/7af778cbdb50617559dcca32514aee3432c3ab09/2-Figure1-1.png "PDF] A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead | Semantic Scholar")
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